1) Field of the Invention
The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.
2) Description of the Prior Art
Typically, Cu interconnects are fabricated using damascene processing methods. In these structures, the top surface of the Cu damascene line is capped with a thin dielectric layer, e.g. Si3N4, SiC, etc, while the bottom surface and two sidewalls are sealed with a metal liner, e.g. TiN, Ta, TaN, etc. Although the fast diffusion paths in Cu interconnect can vary depending on the fabrication process and materials used, all investigators have reported that the electromigration lifetime of Cu transport at interfaces, especially the Cu/dielectric interface. Even though, this interface allows fast diffusion, interjecting a thin conducting layer on the surface of Cu line shows to reduce Cu interface mass transport and enhances Cu electromigration (EM) lifetime.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,777,811: —Harada—Semiconductor device and its fabrication method—Semiconductor device has copper silicide layer formed selectively on copper wiring above which titanium nitride film is deposited inside a hole formed in silicon oxide and silicon nitride films.
U.S. Pat. No. 6,181,013—Liu, Chung-Shi—Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby—Thin film electronic device for use in ultra large scale integrated applications includes a passivation layer overlying an exposed surface of a damascene copper conductor.
U.S. Pat. No. 5,893,752: —Inventor: Zhang, Jiming; Austin, Tex. —Process for forming a semiconductor device—Manufacture of a semiconductor device with metal interconnects
U.S. Pat. No. 6,660,634 Ngo, et al. Dec. 9, 2003—Method of forming reliable capped copper interconnects.
U.S. Pat. No. 5,447,887 Filipiak, et al. Sep. 5, 1995—Method for capping copper in semiconductor devices.
U.S. Pat. No. 6,674,167 Ahn, et al. Jan. 6, 2004—Multilevel copper interconnect with double passivation—forms a silicide layer around the cu interconnects.
U.S. Pat. No. 5,510,295 Cabral, Jr., et al. shows a process to make metal silicide.